1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same and, more particularly, to a semiconductor memory device having gate electrode layers of multistage structure such as an EPROM (electrically programmable read only memory) or EEPROM (electrically erasable and programmable read only memory) in which the control gate electrode is of superposed-layer structure of a polysilicon layer and a refractory metal layer (a high melting point metal layer) or a silicide layer thereof.
2. Description of the Related Art
Conventionally, an EPROM cell is formed by a method as shown in FIGS. 1A-1C.
As shown in FIG. 1A, a field oxide film 2 serving as an element isolation region is formed on a major surface of a p-type silicon substrate 1 to form island regions used as element forming regions. A first gate oxide film 4 is formed on the island regions of the substrate 1. A first polysilicon layer 5 serving as a first level gate electrode (floating gate electrode) is formed on the resultant semiconductor structure.
Thereafter, as shown in FIG. 1B, the polysilicon layer 5 is patterned to form floating gate electrodes 6. By the patterning, a channel or groove 9 is formed between adjacent floating gate electrodes 6. The resultant semiconductor structure is thermally oxidized to form a second gate oxide film 7.
Thereafter, as shown in FIG. 1C, a second polysilicon layer serving as a second level gate electrode (control gate electrode) is formed on the resultant semiconductor structure and patterned to form a control gate electrode 8.
Thereafter, though not shown, an n-type impurity is ion-implanted in the substrate using the control gate 8 as a mask and activated to form n.sup.+ -type source and drain regions. Thereafter, a CVD-SiO.sub.2 film, a contact hole, and an Al wiring layer are sequentially formed, thus manufacturing a EPROM cell.
With the above conventional method, however, the second polysilicon layer has a recess above the separating groove 9. In recent years, in order to increase the operation speed of an element, a refractory metal layer (a high melting point metal layer) or the silicide layer thereof is formed on the second polysilicon layer. However, when a refractory metal layer or the silicide layer thereof is superposed on the second polysilicon layer, the metal layer or the silicide layer has the recess above the separating groove 9. Therefore, when the semiconductor structure is subjected to thermal heating at a later step, the metal layer or the silicide layer often cracks at the step portions of the recess because of a mechanical stress, resulting in disconnection of the metal layer or the silicide layer.
Furthermore, when these layers are formed by a general method such as a sputtering method, the sputtering cannot be performed in the groove with sufficient uniformity, and the thickness of the film may be decreased to increase the resistance thereof.
Moreover, when the control gate layer is etched, the refractory metal or the refractory metal silicide layer and the first polysilicon layer are etched. In this case, when the refractory metal layer or the refractory metal silicide layer and the first polysilicon layer are etched, etching conditions are preferably often changed from a point of view of an etching shape and selectivity of the an underlying insulating film. In this case, if the groove is filled with the refractory metal or the refractory metal silicide, since the refractory metal or the refractory metal silicide layer located at the step portion of the groove is removed by etching, over-etching must be sufficiently performed especially when anisotropic etching is used. Therefore, during this over-etching, the flat underlying polysilicon layer may be disadvantageously etched.